1. Field of the Invention
The present invention relates to a lateral double diffusion MOSFET and a semiconductor device using the same, and more particularly to a lateral double diffusion MOSFET having a high Electro-static discharge performance (ESD) and low on-resistance.
2. Description of the Related Art
Lateral double diffusion MOSFETs, called L-DMOSs, are known for the FETs of ICs and discrete devices, which are generally used in a relatively low voltage region of 100V or lower. The lateral double diffusion MOSFET may be formed by normal diffusion process, and unlike the vertical double diffusion MOSFET, allows all the terminals to be drawn out from the chip top surface. Therefore, it is fit for use in IC fabrication, and is widely used where low on-resistance is required. FIG. 5 is a cross sectional view perspectively showing a conventional lateral double diffusion MOSFET. In the lateral double diffusion MOSFET (referred to as an L-DMOSFET), a drain region 103 is formed by epitaxially growing an N-type semiconductor layer on a P-type semiconductor substrate 101 with an N+ type buried region 102 being interposed therebetween. An N-type impurity is diffused into the drain region 103 to thereby form an N+ type drain contact region 104, and a P-type impurity is diffused into the drain region to thereby form a body region 105. An N+-type source region 106 is formed in a surface region of the body region 105, while being spaced apart from an outer edge of the body region 105. A P+-type region 107 is formed on the inner side of the N+-type source region 106. A drift channel region is formed between the N+-type source region 106 and the N+ type drain contact region 104. A gate electrode is provided covering a surface region ranging from an outer edge part of the N+-type source region 106 to the inner edge part of the drift channel region, while a gate oxide film is interposed therebetween.
This kind of L-DMOSFET is low in on-resistance (operating resistance), although its withstand voltage is high, when comparing with a normal MOSFET. The L-DMOSFET is frequently used in a broad voltage range from several V to 100V, and in particular in power source ICs and motor drivers, it is widely used.
The L-DMOSFET, as shown in FIG. 6, is inevitably accompanied by a parasitic NPN transistor (having an NPN structure including a drain region 103, a body region 105 and the N+-type source region 106), however. This parasitic NPN transistor frequently binders various normal operations of the L-DMOSFET.
When the L-DMOSFET is used in an open drain state, static electricity is applied to the output terminal (drain), the static electricity is trapped, and its entire current flows within the L-DMOSFET. At this time, the parasitic NPN transistor operates as in a positive feedback mode with respect to temperature. As a result, current concentrates at a weak part of the transistor, which was formed during its manufacturing process. And the device will easily be broken.
To improve the breakdown strength, attempt is made to reduce a gain of the parasitic NPN transistor or to additionally use a protection circuit. However, if the gain of the parasitic NPN transistor is reduced, the characteristic of the L-DMOSFET is degraded. If the protection circuit is additionally used, a chip area is increased.
An insulated gate bipolar transistor (IGBT) is well known for a semiconductor element having an extremely high resistance to the static electricity. As shown in FIG. 7, the IGBT has a structure in which the N+ type drain contact region 104 of the L-DMOSFET shown in FIG. 5 is substituted by a P+-type drain contact region 110.
As shown in FIG. 8, the IGBT is attendant with a parasitic thyristor (an NPN transistor formed with a drain region 103, a body region 105 and an N+-type source region 106, and a PNP transistor formed with the body region 105, a drain region 103 and the P+-type drain contact region 110). When an excessive current as by the static electricity flows through the IGBT, the parasitic thyristor is turned on, and the IGBT can process large current with extremely low operating resistance value. Accordingly, the IGBT has an extremely high Electro-static discharge performance (ESD).
In the IGBT, a conductivity of the drain region 103 is varied to reduce a resistance component by positive holes that are injected into the drain region 103 from the P+-type drain contact region 110, which is formed by diffusing a P-type impurity into the drain region (collector) 103. Accordingly, the IGBT is frequently used as a high voltage withstanding element of 100V or higher and having a relatively long drift length (d). The IGBT is a punch-through device. Accordingly, it is impossible to set the drift length to be too long. Accordingly, it is rare that the IGBT is used in a relatively low voltage region of 100V or lower. There is no advantage to integrating an IGBT into an IC rather than an L-DMOSFET. Therefore, the use of an IGBT in such a case is increasingly rare.
A loss of the Vf (forward voltage) value of the IGBT is large at an initial stage of its start. Therefore, in a low current region, the on-resistance of the IGBT is higher than that of the L-DMOSFET, and the IGBT has many disadvantages. Further, in a large current region, the latch-up of the parasitic thyristor is easy to occur. Accordingly, care must be taken for use conditions. Further, minority carriers take part in the operation of the IGBT. Accordingly, the frequency characteristic of the IGBT is inferior to that of the L-DMOSFET. This also is recognized as a large defect of the IGBT.
As described above, the conventional L-DMOSFET is advantageous in that it is easy to attain a high voltage standing performance and is low in on-resistance, but is disadvantageous in that the Electro-static discharge performance (ESD) is low. The IGBT is advantageous in that its Electro-static discharge performance (ESD) is extremely high, but has many disadvantages: For example, it is not suitable for high integration; the on-resistance is high in a low current region; and the frequency characteristic is bad.